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| 同步JK触发器门级建模仿真讨论 |
| Further Discussion of Synchronous JK Flip-flop and Verilog HDL Simulation |
| 投稿时间：2021-04-14 修订日期：2021-08-23 |
| DOI： |
| 中文关键词: 同步JK触发器 数字系统与逻辑设计 Vivado仿真 Verilog HDL仿真 |
| 英文关键词: Synchronous JK Flip-flop Digital system and logic design Vivado simulation Verilog HDL simulation |
| 基金项目:2019年国防科技大学“金课”导向的“数字电路与逻辑设计”课程建设研究与实践项目；2019年国防科技大学成果立项培育:“数字电路与逻辑设计”课程立体化教学改革与实践 |
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| 中文摘要: |
| 同步JK触发器是“数字电路与逻辑设计”课程中重要的一种触发器单元。但目前教材给出的同步JK触发器的翻转状态是值得商榷的。关于同步JK触发器的仿真方面，网上的一些资料较为混乱，很多资料上对于JK触发器直接采用教科书上的结论进行行为级建模，虽然避免了初始状态的影响，但并不能真正反应JK触发器的真正功能。也有人采用与非门例化的方法对其进行门级建模，但仿真输出一直为一个不确定的状态。本文通过加入复位信号，使得触发器的当前状态为一个确定状态，从而能正确仿真。仿真和分析表明，翻转状态是值得商榷的，教科书也应据此进行更改。 |
| 英文摘要: |
| Synchronous JK flip-flop is an important flip-flop unit in the course of digital circuit and logic design. But the flipped state of synchronous JK flip-flop given in the current textbook is questionable. On the simulation of synchronous JK flip-flop, some materials on the internet are confusing. Many materials directly use the conclusions of textbooks for behavioral modeling of JK flip-flop. Although it avoids the influence of initial state, it does not really reflect the real function of JK flip-flop. Some people use the method of nand gate instantiation for gate level modeling, but the simulation output is always in an uncertain state. In this paper, by adding Reset signal, the current state of the flip-flop is a certain state, so that it can simulate correctly. Simulation and analysis show that the flipped state is questionable, and textbooks should be changed accordingly. |
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